1. Field of the Invention
Exemplary embodiments of the present invention relate to wiring structures of a semiconductor device, methods of forming such wiring structures, non-volatile memory devices including such a wiring structure, and methods of manufacturing such a non-volatile memory device. More particularly, exemplary embodiments of the present invention relate to wiring structures of a semiconductor device that has an increased contact margin with respect to a contact plug on the wiring structure, methods of forming the wiring structure, non-volatile memory devices including such a wiring structure, and methods of manufacturing such a non-volatile memory device.
2. Description of the Related Art
Generally, memory devices may be classified as volatile memory devices or non-volatile memory devices based on whether the memory devices stores or removes data when current is not provided to the memory device. Examples of volatile memory devices may include erasable programmable read only memory (EPROM) devices, electrically EPROM (EEPROM) devices, flash memory devices, etc. Merits of EPROM and EEPROM are embedded in the flash memory. That is, the flash memory generally uses a process substantially the same as that of the EPROM when data is programmed and the flash memory generally uses a process substantially the same as that of the EEPROM when the data is erased. Further, the flash memory generally has a smaller chip size than those of the EPROM and the EEPROM, and thus, the flash memory may have a higher capacity. Furthermore, information in the flash memory may be immediately renewed through a system.
Flash memories may be classified as a NOR type flash memory or a NAND type flash memory in accordance with constitutions of a cell. A memory cell of the NAND type flash memory may include cell strings in a cell array to which, e.g., sixteen or thirty-two cell transistors are connected. A string selection transistor for selecting strings may be connected to one end of each of the cell strings. Further, a ground selection transistor may be connected to the other end of each of the cell strings.
Gate electrodes of each of the string selection transistors may be connected to each other. The gate electrodes of the string selection transistors may serve as a string selection line (SSL). Further, gate electrodes of each of the ground selection transistors may be connected to each other. The gate electrodes of the ground selection transistors may serve as a ground selection line (GSL).
A common source line may be electrically connected to source regions of the ground selection transistors. The common source line may extend in a direction substantially perpendicular to an extending direction of the cell strings. Further, a contact plug and a bit line may be formed on the common source line so that the contact plug and the bit line may be electrically connected to the common source line.
In the above-mentioned memory cell of the NAND type flash memory, the contact plug must be accurately formed on the common source line. Thus, a process for forming a contact hole may be carried out in advance to precisely expose an upper surface of the common source line through the contact hole.
However, when the contact hole is misaligned during, e.g., a photolithography process for forming the contact hole, the common source line may not be exposed through the misaligned contact hole so that an insulation interlayer on a sidewall of the common source line may be etched. Further, the misaligned contact hole may partially expose an upper surface of a semiconductor substrate adjacent to the common source line. As a result, a short between the contact plug in the misaligned contact hole and, e.g., the exposed upper surface of the semiconductor substrate or a gate of an adjacent transistor may be generated.